Design-Reuse

Advanced Techniques for IP Design and Verification

As designs grow in size and complexity, the challenges associated with low power and the growing design and verification gap have created the need for a paradigm shift in the IP design and ...
EDN

Verilog design tool supports encrypted IP

VeriLogger Extreme, a compiled-code Verilog simulation and debugging environment, now features support for encrypted IP models from all the major ASIC/FPGA vendors. The package supports both ...
Design-Reuse

Efficient Verification and Virtual Prototyping of Analog and Mixed-Signal IP and SOCs Using Behavioral Models

This paper describes the use of behavioral models and mixed-signal simulation as a means to verify the proper instantiation, connectivity and control of analog and mixed-signal (AMS) intellectual ...
Semiconductor Engineering

Why Every Design IP Needs A Complete QA Methodology

Design IP is a key contributor to innovation in the semiconductor industry today. As the complexity and scale of silicon designs increase, so does design and verification time. Design IP enables ...
EDN

Speed compile/verification under Synopsys VCS

At the same time as the number of transistors on your average chip doubles every 18 months, the verification cycle has shrunk from 18 to 12 months, which in the near future will become as low as six ...
Electronic Design

What’s the Difference Between VHDL, Verilog, and SystemVerilog?

Designers of electronic hardware describe the behavior and structure of system and circuit designs using hardware description languages (HDLs)—specialized programming languages commonly known as VHDL, ...