Systems on chip (SoC) and processor design teams are challenged to meet aggressive power, performance and area requirements. As chip complexity grows, teams must verify thousands of lines of code to ...

Clock gating is one of the most frequently used techniques in RTL to reduce dynamic power consumption without affecting the functionality of the design. One method involves inserting gating conditions ...

While production schedules keep getting squeezed, managing power consumption takes more of a designer's time. As a result, finding ways to reduce power in chips, while minimizing design-cycle impact, ...

As the cost of failure continues to rise, SoC engineers see the growing importance of ensuring their work is as correct as possible as soon as possible in the design process. They cannot afford to ...

In this paper, we examine the need for formal sequential equivalence checking across pairs of RTL models. We present scenarios that call for modifying the sequential behavior of RTL models while ...

Dealing with power is a multifaceted challenge and is an equal-opportunity problem — everybody can contribute to the solution and at many levels of abstraction. At the architectural or system level, ...

Unlike combinational power reduction tools, PowerPro CG identifies and generates sequential clock-gating transformations. It fits into existing design flows with industry-standard library, timing, and ...